A conventional lead-frame-based semiconductor package, such as QFN (quad flat non-leaded) package, incorporates a semiconductor chip on a lead frame serving as a chip carrier, and exposes leads of the lead frame to outside of an encapsulant that encapsulates the chip, allowing the exposed leads as input/output (I/O) connections to be electrically connected to an external device such as printed circuit board (PCB).
This QFN semiconductor package is disclosed in U.S. Pat. Nos. 6,130,115, 6,143,981 and 6,229,200; as shown in FIG. 6, at least one chip 20 is mounted via an adhesive (not shown) on a die pad 210 of a lead frame 21 and electrically connected to a plurality of leads 211 surrounding the die pad 210 by bonding wires 22. An encapsulant 23 formed of a resin material (such as epoxy resin) encapsulates the chip 20, bonding wires 22, and lead frame 21, with at least one surface 212 of each lead 211 being exposed to outside of the encapsulant 23.
As shown in FIG. 7A, since the leads 211 of the lead frame 21 is substantially proportional in number to bond pads 201 formed on an active surface 200 of the chip 20, each bond pad 201 is electrically connected via a bonding wire 22 to a corresponding lead 211. The leads 211 are spaced apart from the die pad 210 by a predetermined distance, such that the bonding wires 22 need to be greater in length than the distance between the leads 211 and die pad 210 so as to effect successful electrical connection between the chip 20 and leads 211. As shown in FIG. 7B, in the case of using a highly integrated chip 20′ having more bond pads 201 or higher density of bond pads 201, more leads 211 are accordingly required for electrical connection with the bond pads 201, thus making the distance between the leads 211 and die pad 210 and the length of bonding wires 22′ increased. Long bonding wires 22′, however, make a wire bonding process harder to implement and are easily subject to wire sweep or shift due to resin flow impact in a molding process for forming the encapsulant 23. The swept or shifted bonding wires may accidentally come into contact with each other and cause short circuits, which would undesirably degrade quality of electrical connection. Further, if the leads and die pad are spaced apart from each other too far, the wire bonding process may even be impossibly performed and thus fails to use bonding wires to electrically connect the chip to the leads of the lead frame.
In order to reduce the length of bonding wires or the distance between the leads and die pad, as shown in FIG. 8, another semiconductor package is produced in which each lead 211 is half-etched to form a protruding portion 213 extending toward the die pad 210 so as to reduce the distance between the leads 211 and die pad 210, such that bonding wires 22 with proper length can be used to electrical connect the highly integrated chip 20′ to the protruding portions 213 of the leads 211.
However, fabrication of the protruding portions 213 would undesirably increase costs and process complexity for making the lead frame 21′. And, during the wire bonding process, the protruding portions 213 of the leads 211 may easily dislocate in position, making it hard to precisely bond the bonding wires 22 thereto.
U.S. Pat. Nos. 5,830,800 and 6,072,239 provide a semiconductor package free of using a substrate, whose fabrication processes are primarily illustrated with reference to FIGS. 9A to 9D. Referring to FIG. 9A, the first step is to prepare a copper-made carrier 30 and mount a mask 31 over a surface of the carrier 30, wherein the mask 31 is formed with a plurality of openings 310 via which predetermined portions of the carrier 30 are exposed. Referring to FIG. 9B, the next step is to electrically plate a contact (or terminal) 32 in each of the openings 310 and then to remove the mask 31 from the carrier 30 to expose the carrier 30 and contacts 32. Referring to FIG. 9C, a die bonding process and a wire bonding process are in turn performed by which a chip 33 is mounted on the carrier 30 and electrically connected to the contacts 32 by a plurality of bonding wires 34. Then, a molding process is carried out to form an encapsulant 35 on the carrier 30 for encapsulating the chip 33 and bonding wires 34. Referring to FIG. 9D, the carrier 30 is etched away to expose surfaces 320, originally in contact with the carrier 30, of the contacts 32, and the exposed contacts 32 serve as input/output (I/O) connections of the semiconductor package to be electrically connected to an external device (not shown).
The above semiconductor package yields a significant benefit as not having to use a substrate or lead frame for accommodating chips; as a result, the encapsulant 35 is not attached to the above-mentioned lead frame 21 and there is no concern of delamination between the encapsulant 35 and lead frame 21. However, similarly to the previously discussed packaging technology, in the case of using a highly integrated chip 33 with more bond pads or higher density of bond pads, more contacts 32 are accordingly required and undesirably increase the distance between the contacts 32 and chip 33, thereby causing the similar problems as shown in FIG. 7B that long bonding wires are subject to wire sweep or shift and degrade quality of electrical connection.
Therefore, the problem to be solved herein is to provide a semiconductor package which can flexibly arrange conductive traces and effectively shorten bonding wires so as to improve trace routability and quality of electrical connection for the semiconductor package.